I. Field of the Disclosure
The technology of the disclosure relates to metal oxide semiconductors (MOS).
II. Background
Mobile communication devices have become common in current society. The prevalence of these mobile devices is driven in part by the many functions that are now enabled on such devices. Demand for such functions increases processing capability requirements and generates a need for more powerful batteries. Within the limited space of the housing of the mobile communication device, batteries compete with the processing circuitry. These and other factors contribute to a continued miniaturization of components and power consumption within the circuitry. Miniaturization of components impacts all aspects of the processing circuitry, including the transistors and other reactive elements in the processing circuitry including metal oxide semiconductors (MOS).
Historically MOS devices have benefited from increasing miniaturization efforts, for example, advancing from 0.25 micrometer (μm) scale down through 0.13 λm to a twenty-eight (28) nanometer (nm) scale, with current efforts working on a twenty (20) nm scale. Such semiconductor miniaturization not only reduced the footprint area occupied by the MOS devices in an integrated circuit (IC), but also reduced the power required to operate such IC and concurrently improved operating speeds. As the MOS devices are reduced to a nanometer scale, for example, ninety (90) nm scale, the footprint area occupied by the MOS devices in the IC was reduced as expected. However, the MOS devices could not operate at an appreciably faster speed, because the mobility of the current mechanism (i.e., electrons or holes) did not also improve linearly because the mobility is a function of the effective mass of the current mechanism, and the effective mass was not changing with the miniaturization.
Additionally, existing MOS devices have relied on shallow trench isolation (STI) between active elements to provide desired isolation between the devices. However, as the miniaturization reaches the nanometer scale, STI takes up valuable space within the IC.
Various techniques have been implemented to attempt to improve the speed with which MOS devices operate in the nanometer scale. One example includes introducing stress on the MOS channel element to improve mobility of the current mechanism. Stress inducing elements rely on physical dimensions of the stressor to provide the stress. That is, to introduce a large stress to improve mobility, a physically large stressor is used, which conflicts with the miniaturization goals. Additionally, STI interferes with the formation of stressors, reducing the physical dimensions of the stressor that is available to provide the desired stress.
At least one proposed solution to avoid reduced performance associated with the reduction of stress inducing elements was the elimination of the STI breaks with a continuous active area. Instead of the STI breaks, a dummy gate has been inserted between components. However, the isolation provided by such dummy gates has been worse than the isolation provided by STI and/or it requires higher gate bias, which in turn has its own problems such as requiring a power rail, increasing cost and increasing the footprint of the device. Thus, there needs to be an effective isolation technique through which adjacent MOS devices may operate without degradation.